On 04/06/2018 08:41 AM, Jonathan Cameron wrote:
On 6 April 2018 16:21:05 BST, Jean-Baptiste Maneyrol <JManeyrol@xxxxxxxxxxxxxx> wrote:
Hello,
there is just a problem if I'm understanding well.
Reading FIFO count register under hard irq handler (when taking the
timestamp) is not possible since i2c access is using a mutex. That's
why we are using an irq thread for reading FIFO content.
Good point. Need more sleep or caffeine!
I was about to reply with the same, as I started coding it up :). Too
bad, it was such a great plan!
I have a little update: When switching to level triggered interrupts,
the problem goes away for me, as do the bus errors I get at high
frequencies. I'm working on a patch to support other interrupt types
than rising edge, which is almost done.
I also intend to look again at the bus errors for edge driven
interrupts. Since they happen only at high frequency and go away with
level driven interrupts (which must be acked and therefore prevent
reentrancy), I suspect there's a concurrency bug.
That said, I think the question remains: Since we can't get the FIFO
count from the hard IRQ handler, and since it could be some time before
the bottom half thread is scheduled, I don't see any way to accurately
handle forward interpolation.
Though we can't do forward interpolation, I think at least having
backward interpolation is better than filling in blank timestamps,
especially as we haven't seen an actual case of forward interpolation
being needed, while we have real use cases that require backward
interpolation (and can be easily verified in a logic analyzer).
However, that's only my opinion. Jonathan, Jean-Baptiste, and others,
what do you think?
I've been able to reproduce the issue when doing a long stress-test at
high speed (200Hz). Perhaps this is related to the FIFO error handling
which looks really over-complex for me. I am currently investigating
this issue.
But I would be happy to test any new solution if proposed.
Best regards,
JB
Thanks Jean-Baptiste; let me know how that turns out.
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