2017-01-14 18:49 GMT+01:00 Lars-Peter Clausen <lars@xxxxxxxxxx>:
> On 01/14/2017 06:18 PM, Matthias Klumpp wrote:
>>> The IIO framework itself does not impose a limit on the maximum sampling
>>> rate. It's all a matter of what the hardware is capable of handling. We have
>>> systems where we do 3-digit MSPS continuous transfers and GSPS oneshot
>>> transfers.
>>
>> Since this is the first time I touched this area: Is there a group of
>> chips which you would recommend that samples with 200ksps, has a 16bit
>> bit-depth and bipolar mode and is accessible at that speed via IIO?
>> I'll look around a bit to find a solution for this issue.
>
> Unfortunately this is often as much about the AP as it is about the
> converter. In the setups we have we use a AP+FPGA combination where the AP
> runs Linux with IIO and the FPGA is responsible for handling the SPI flow
> control during the acquisition phase. For this we've developed the
> SPI-Engine framework[1]. It is compatible with most ADI single-channel SAR
> and Sigma-Delta ADCs[2].
> [...]
Thanks!
I was already looking into this, but also tried to access the BCM2835
on my Raspberry Pi test device directly (someone wrote a nice helper
library for that at [1]).
Turns out that using this library, I can easily achieve my desired
speed of 200ksps (it also turned out that with a few changes on the
setup, 6ksps can be just enough...).
Maybe the kernel abstraction is causing the delays I was experiencing,
or maybe my kernel driver is simply not optimized enough (it could
read multiple samples in batches).
If I find the bottleneck, I'll let you know...
Meanwhile, I am glad that I apparently got around making an FPGA-based
controller, that would have been a lot more work.
Regards,
Matthias
[1]: http://www.airspayce.com/mikem/bcm2835/
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