On 01/14/2017 06:18 PM, Matthias Klumpp wrote: >> The IIO framework itself does not impose a limit on the maximum sampling >> rate. It's all a matter of what the hardware is capable of handling. We have >> systems where we do 3-digit MSPS continuous transfers and GSPS oneshot >> transfers. > > Since this is the first time I touched this area: Is there a group of > chips which you would recommend that samples with 200ksps, has a 16bit > bit-depth and bipolar mode and is accessible at that speed via IIO? > I'll look around a bit to find a solution for this issue. Unfortunately this is often as much about the AP as it is about the converter. In the setups we have we use a AP+FPGA combination where the AP runs Linux with IIO and the FPGA is responsible for handling the SPI flow control during the acquisition phase. For this we've developed the SPI-Engine framework[1]. It is compatible with most ADI single-channel SAR and Sigma-Delta ADCs[2]. - Lars [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine [2] http://www.analog.com/en/products/analog-to-digital-converters/precision-adc-10msps/single-channel-ad-converters.html -- To unsubscribe from this list: send the line "unsubscribe linux-iio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
