On Fri, Mar 27, 2015 at 11:06 AM, Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> wrote: > On Thu, Mar 26, 2015 at 06:28:19PM +0200, Octavian Purdila wrote: >> For the sleep case I think the GPIO controller needs to do the pin >> enable and set input direction operation in it's irq_bus_sync_unlock. > > I wonder how DT handles all this? Is it the boot firmware that sets up > the pins accordingly or is there something we are missing? DT systems mostly do not have firmware for power usecases, they handle it all using pin control. I would more say that is a feature of all-SW systems without power-firmware ideas, without ACPI and without PSCI (well PSCI systems do not care about much more than CPU power down in firmware anyway...) Sometimes the power-down/up path includes driving pins to GND using the generic pin config option PIN_CONFIG_OUTPUT to drive the logic. For details on this mess where HW designers think that low-power sleep mode is "GPIO-something" see Documentation/pinctrl.txt section named "GPIO mode pitfalls". I..e the question is not what registers are involved and what these are named, but the actual usecase. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-iio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html