Hi Lars, On Thu, 18 Jul 2013 15:54:03 +0200 Lars-Peter Clausen <lars@xxxxxxxxxx> wrote: > On 07/18/2013 02:02 PM, Otavio Salvador wrote: >> On Thu, Jul 18, 2013 at 2:50 AM, Lars-Peter Clausen <lars@xxxxxxxxxx> wrote: >>> >>> Well the standard API as Jonathan said is to expose all possible pin >>> combinations. In this case that might be up to 8x8=64 channels. In my >>> opinion that's fine, but on a specific board maybe not all combinations are >>> valid. So you might want to specify in your platform data or devicetree that >>> only a subset of these 64 channels is valid and should be exposed to >>> userspace. In my opinion it makes the most sense to handle this in the IIO >>> core since this is a generic requirement, nothing specific to this chip. >>> E.g. even for 'simple' converters you'll find situations where some pins >>> might not be connected. >> >> Right and how should we do this? >> >> Because it would not be 8x8 but it has also the single-ended >> combinations (using different N inputs). > > Does the device really support single ended, it looks to me as if it only > supports pseudo-differential configurations. That's not very clear to me either. The datasheet states the chips have single-ended inputs, but the mux configuration always assume a positive input and a negative input. I'm assuming the "single-ended" mode refers to using an arbitrary input as negative reference to all the other n-1 inputs. I suppose that'd be a pseudo-differential configuration, right? Best wishes. Mario -- To unsubscribe from this list: send the line "unsubscribe linux-iio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
