Re: voltage and current regulator framework: specifying negative voltages

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On Thu, Apr 14, 2011 at 12:44:43PM +0200, Michael Hennerich wrote:
> On 04/13/2011 07:24 PM, Mark Brown wrote:

Please cut irrelevant context from your replies.

> >>> Updating the core to allow negative and zero voltages, is not  straight
> >>> forward.
> >>> There are more issues with constrain checking and I currently can't
> >>> oversee all side

> > What are the issues that you see?

> In case the output voltage can be negative, the input voltage may be
> negative as well.
> In functions drms_uA_update() and regulator_set_optimum_mode(), the
> input supply voltage
> is checked for being > 0, if that fails it uses the constrains->input_uV
> instead...

None of this seems particularly complicated to deal with, it's not a
massive change in the architecture of the code or anything - it's all
just refactoring interfaces and implementations a bit.

> BTW: Function drms_uA_update() looks suspicious.

>     /* get input voltage */
>     input_uV = 0;
>     if (rdev->supply)
>         input_uV = _regulator_get_voltage(rdev);

> it checks for rdev->supply but later uses rdev, which will ultimately
> mean input_uV == output_uV.

There's very few users of supplies in mainline and no users at all of
the optimal mode stuff.
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