different ring buffer usage scenario

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Hi Jonathan,

I'm currently working on a high speed ADC driver, that requires a different ring buffer use case scenario.
Let me explain a little bit the setup. I'm running Linux on a Microblaze softcore inside an Virtex6 FPGA.
Part of the system is a peripheral interface block, we call it the ADC Interface Module (AIM).
External to the FPGA we connect a single channel high speed ADC AD9649, to the AIM signals.

The AIM features a FIFO, with watermark interrupt capabilities. There are two modes that need to be supported.
Continues Sampling Mode and Single Shot Sample Mode. In Single Shot Sample Mode, the user reads an arbitrary
Number of samples from the ADC, and then the sampling stops. This mode does not need to have a ringbuffer at all.
A simple chardev might be sufficient.

Any objections creating a driver private chardev?

In Continues Sampling Mode we store continuously data into the ringbuffer, and assume that userspace reader can catch up.
Now looking at the existing sw_ring, we don't need the scan element concepts, no timestamps and bytes_per_datum is going to be used in a different fashion.
Ideally bytes_per_datum defaults to the ADC width. However right now it is used to set the number of bytes stored into the ring by a call to ring->access.store_to().
bytes_per_datum currently must be constant while the ring is enabled.
However we need to store an arbitrary number of elements into the buffer.

Following example:
The AIM internal fifo can hold 512 elements, we set the fifo almost full watermark to 400 elements. In the ISR we read the number of elements that are currently in the fifo. This number will be > the fifo almost full watermark (e.g. 400 elements) but likely less than the fifo size.

Do you think it is possible to modify iio_store_to_sw_ring(), without breaking the implementation, to support this kind of use?

Greetings,
Michael

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