On Mon, Sep 25, 2023 at 5:27 PM Damien Le Moal <dlemoal@xxxxxxxxxx> wrote: > > On 2023/09/25 11:13, Mika Westerberg wrote: > > Hi, > > > > On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: > >> On 2023/09/25 10:05, Mika Westerberg wrote: > >>> Intel Alder Lake-P AHCI controller needs to be added to the mobile > >>> chipsets list in order to have link power management enabled. Without > >>> this the CPU cannot enter lower power C-states making idle power > >>> consumption high. > >>> > >>> Cc: Koba Ko <koba.ko@xxxxxxxxxxxxx> > >>> Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > >> > >> Looks OK, but given that there is a tendency of the low power stuff to be buggy, > >> was this well tested ? > > > > Yes it was tested (Koba Cc'd can confirm this). We also confirmed from > > Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support > > this configuration. I verified on an ADL platform with odd and disk devices and they work fine. > > > >> Also, does this need a Fixes/CC stable tag ? If not, I > >> will queue this for 6.7. > > > > Up to you :) Typically PCI ID additions can go to stable as well. No > > fixes tag needed, though (there is no commit that this one fixes). > > OK. I will not add a CC stable for now. If requested, we can trivially backport > this later. > > > > > Thanks! > > -- > Damien Le Moal > Western Digital Research >
