On Mon, 2017-05-08 at 10:36 +0200, Ricard Wanderlof wrote: > On Mon, 8 May 2017, David Woodhouse wrote: > > Our empirical testing trumps your "can never happen" theory :) > > I'm sure it does. But what is the explanation then? Has anyone analyzed > what is going on using an oscilloscope to verify relationship between > erase command and supply voltage drop? Not that I'm aware of. Once we have reached the "it does happen and we have to cope" there was not a lot of point in working out *why* it happened. In fact, the only examples I *personally* remember were on NOR flash, which takes longer to erase. So it's vaguely possible that it doesn't happen on NAND. But really, it's not something we should be depending on and the software mechanisms have to remain in place.
Attachment:
smime.p7s
Description: S/MIME cryptographic signature
