tree: https://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git for-4.11 head: ef774e3dca9df8b34367aa9d9fca2c1c08fcde7d commit: ef774e3dca9df8b34367aa9d9fca2c1c08fcde7d [24/24] ahci: qoriq: added ls2088a platforms support config: i386-randconfig-x005-201703 (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: git checkout ef774e3dca9df8b34367aa9d9fca2c1c08fcde7d # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): In file included from include/linux/linkage.h:4:0, from include/linux/kernel.h:6, from drivers/ata/ahci_qoriq.c:13: drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_phy_init': drivers/ata/ahci_qoriq.c:194:12: error: 'struct ahci_qoriq_priv' has no member named 'is_dmacoherent' if (qpriv->is_dmacoherent) ^ include/linux/compiler.h:149:30: note: in definition of macro '__trace_if' if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ^~~~ >> drivers/ata/ahci_qoriq.c:194:3: note: in expansion of macro 'if' if (qpriv->is_dmacoherent) ^~ drivers/ata/ahci_qoriq.c:194:12: error: 'struct ahci_qoriq_priv' has no member named 'is_dmacoherent' if (qpriv->is_dmacoherent) ^ include/linux/compiler.h:149:42: note: in definition of macro '__trace_if' if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ^~~~ >> drivers/ata/ahci_qoriq.c:194:3: note: in expansion of macro 'if' if (qpriv->is_dmacoherent) ^~ drivers/ata/ahci_qoriq.c:194:12: error: 'struct ahci_qoriq_priv' has no member named 'is_dmacoherent' if (qpriv->is_dmacoherent) ^ include/linux/compiler.h:160:16: note: in definition of macro '__trace_if' ______r = !!(cond); \ ^~~~ >> drivers/ata/ahci_qoriq.c:194:3: note: in expansion of macro 'if' if (qpriv->is_dmacoherent) ^~ vim +/if +194 drivers/ata/ahci_qoriq.c 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 */ 12 > 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pm.h> 16 #include <linux/ahci_platform.h> 17 #include <linux/device.h> 18 #include <linux/of_address.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/libata.h> 23 #include "ahci.h" 24 25 #define DRV_NAME "ahci-qoriq" 26 27 /* port register definition */ 28 #define PORT_PHY1 0xA8 29 #define PORT_PHY2 0xAC 30 #define PORT_PHY3 0xB0 31 #define PORT_PHY4 0xB4 32 #define PORT_PHY5 0xB8 33 #define PORT_AXICC 0xBC 34 #define PORT_TRANS 0xC8 35 36 /* port register default value */ 37 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 38 #define AHCI_PORT_TRANS_CFG 0x08000029 39 #define AHCI_PORT_AXICC_CFG 0x3fffffff 40 41 /* for ls1021a */ 42 #define LS1021A_PORT_PHY2 0x28183414 43 #define LS1021A_PORT_PHY3 0x0e080e06 44 #define LS1021A_PORT_PHY4 0x064a080b 45 #define LS1021A_PORT_PHY5 0x2aa86470 46 #define LS1021A_AXICC_ADDR 0xC0 47 48 #define SATA_ECC_DISABLE 0x00020000 49 #define LS1046A_SATA_ECC_DIS 0x80000000 50 51 enum ahci_qoriq_type { 52 AHCI_LS1021A, 53 AHCI_LS1043A, 54 AHCI_LS2080A, 55 AHCI_LS1046A, 56 AHCI_LS2088A, 57 }; 58 59 struct ahci_qoriq_priv { 60 struct ccsr_ahci *reg_base; 61 enum ahci_qoriq_type type; 62 void __iomem *ecc_addr; 63 }; 64 65 static const struct of_device_id ahci_qoriq_of_match[] = { 66 { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A}, 67 { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A}, 68 { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A}, 69 { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A}, 70 { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A}, 71 {}, 72 }; 73 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); 74 75 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, 76 unsigned long deadline) 77 { 78 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 79 void __iomem *port_mmio = ahci_port_base(link->ap); 80 u32 px_cmd, px_is, px_val; 81 struct ata_port *ap = link->ap; 82 struct ahci_port_priv *pp = ap->private_data; 83 struct ahci_host_priv *hpriv = ap->host->private_data; 84 struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data; 85 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 86 struct ata_taskfile tf; 87 bool online; 88 int rc; 89 bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A); 90 91 DPRINTK("ENTER\n"); 92 93 ahci_stop_engine(ap); 94 95 /* 96 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is: 97 * A-009042: The device detection initialization sequence 98 * mistakenly resets some registers. 99 * 100 * Workaround for this is: 101 * The software should read and store PxCMD and PxIS values 102 * before issuing the device detection initialization sequence. 103 * After the sequence is complete, software should restore the 104 * PxCMD and PxIS with the stored values. 105 */ 106 if (ls1021a_workaround) { 107 px_cmd = readl(port_mmio + PORT_CMD); 108 px_is = readl(port_mmio + PORT_IRQ_STAT); 109 } 110 111 /* clear D2H reception area to properly wait for D2H FIS */ 112 ata_tf_init(link->device, &tf); 113 tf.command = ATA_BUSY; 114 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 115 116 rc = sata_link_hardreset(link, timing, deadline, &online, 117 ahci_check_ready); 118 119 /* restore the PxCMD and PxIS on ls1021 */ 120 if (ls1021a_workaround) { 121 px_val = readl(port_mmio + PORT_CMD); 122 if (px_val != px_cmd) 123 writel(px_cmd, port_mmio + PORT_CMD); 124 125 px_val = readl(port_mmio + PORT_IRQ_STAT); 126 if (px_val != px_is) 127 writel(px_is, port_mmio + PORT_IRQ_STAT); 128 } 129 130 hpriv->start_engine(ap); 131 132 if (online) 133 *class = ahci_dev_classify(ap); 134 135 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 136 return rc; 137 } 138 139 static struct ata_port_operations ahci_qoriq_ops = { 140 .inherits = &ahci_ops, 141 .hardreset = ahci_qoriq_hardreset, 142 }; 143 144 static const struct ata_port_info ahci_qoriq_port_info = { 145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, 146 .pio_mask = ATA_PIO4, 147 .udma_mask = ATA_UDMA6, 148 .port_ops = &ahci_qoriq_ops, 149 }; 150 151 static struct scsi_host_template ahci_qoriq_sht = { 152 AHCI_SHT(DRV_NAME), 153 }; 154 155 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) 156 { 157 struct ahci_qoriq_priv *qpriv = hpriv->plat_data; 158 void __iomem *reg_base = hpriv->mmio; 159 160 switch (qpriv->type) { 161 case AHCI_LS1021A: 162 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); 163 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 164 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); 165 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); 166 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); 167 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); 168 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 169 writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR); 170 break; 171 172 case AHCI_LS1043A: 173 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 174 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 175 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 176 break; 177 178 case AHCI_LS2080A: 179 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 181 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 182 break; 183 184 case AHCI_LS1046A: 185 writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr); 186 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 187 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); 188 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 189 break; 190 191 case AHCI_LS2088A: 192 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); 193 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); > 194 if (qpriv->is_dmacoherent) 195 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); 196 break; 197 } --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Attachment:
.config.gz
Description: application/gzip
