Tejun Heo <tj@xxxxxxxxxx> writes:
> On Tue, Apr 26, 2016 at 12:03:04PM +0300, Andy Shevchenko wrote:
>> diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
>> index 7f95389..aee8873 100644
>> --- a/drivers/ata/sata_dwc_460ex.c
>> +++ b/drivers/ata/sata_dwc_460ex.c
>> @@ -1151,7 +1151,13 @@ static struct scsi_host_template sata_dwc_sht = {
>> */
>> .sg_tablesize = LIBATA_MAX_PRD,
>> /* .can_queue = ATA_MAX_QUEUE, */
>> - .dma_boundary = ATA_DMA_BOUNDARY,
>> + /*
>> + * Make sure a LLI block is not created that will span 8K max FIS
>> + * boundary. If the block spans such a FIS boundary, there is a chance
>> + * that a DMA burst will cross that boundary -- this results in an
>> + * error in the host controller.
>> + */
>> + .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
>
> The host controller can't cross 8k boundary? Is this for real?
>From the manual:
DMA block and burst transaction sizes are critical for DMA operation.
(Also see the definition of "DMA transfer".) These sizes should be
selected properly to ensure error-free bus transfers. It is required
that the DMA write burst transfer does not cross the 8192-byte Data
FIS boundary, because the Transport Layer maintains the DMA state for
the duration of the Data FIS transmission.
--
Måns Rullgård
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