From: Jeff Garzik <jgarzik@xxxxxxxxx> Date: Tue, 02 Feb 2010 18:14:40 -0500 > The patch in question only affects PIO transfers, not DMA. Data is > transferred from a kernel buffer to hardware via out[bwl] via > > page data -> CPU register -> out[bwl] > > or, data is transferred from hardware to a kernel buffer via > > in[bwl] -> CPU register -> page data > > So what are the flushing rules given those conditions? Any time you touch a page cache page with the cpu, you have to get it purged from aliasing caches before it gets mapped into userspace or similar. That's the problem on these machines. Actually, sparc64 is probably susceptible to the same problem. And it's not an issue in the IDE layer, know why? :-) In the IDE layer we have arch specific ide_*() interfaces which is where all of this PIO dma flushing stuff deserves to live. ATA should do something similar instead of randomly scattering flush_dcache_page() calls all over the place. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
