> (1b) The solution for MMIO controllers is a bit more complex: replace > the dummy AltStatus register read with something else. If we had any SFF PATA controllers using MMIO. I can't find any. SATA is different anyway. In fact we probably want to avoid such delays on a pure SATA controller. > > SIL680 is MMIO in the old IDE stack but the hardware appears to be doing > > the required magic itself. > > You cannot draw such a conclusion from looking only at the SIL680 chip. > SIL680 might easily be behind a PCI bridge. Not the one I have, nor it appears have there ever been any reports of the problem on any system in years. That problem would show up if it exists. It's also necessary that the chip can do its own timings in some of its fancier modes. The person who has the problem to worry about is Ben, but the older PMAC stuff has its own implementation of all the DMA/IRQ/Command stuff as far as I can see so its not relevant there. Several years and zillions of users say there isn't a problem. The fact we only enable the SIL680 mmio on libata also means its a rather irrelevant discussion in the first place. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
