On Friday 18 September 2009 13:52:50 Sergei Shtylyov wrote:
> Hello.
>
> Jung-Ik (John) Lee wrote:
>
> >>>From: John(Jung-Ik) Lee <jilee@xxxxxxxxxx>
>
> >>>Fix udma timings of pdc202xx_old controllers.
> >>>MB=1, MC=1 (0x20, 0x01) for all UDMA modes of pdc2026{57}.
>
> The patch should be broken in two as it's for 2 different subsystems.
>
> >>On what documentation is this based ?
>
> > I have two documents, 20265, and 20267, and both need to set to the
> > same single value for all UDMA modes.
>
> > Doc 1:
> > PDC20265 Bus Mastering Ultra DMA PCI –ATA/ATAPI Controller
> > Specification Rev 2.0
> > #7.17.2, Ultra DMA Data Transfer Speed list
> > For all Ultra DMA mode, MB, MC = 01h, 01h
>
> > Doc 2:
> > PDC20267 Bus Mastering Ultra DMA PCI –ATA/ATAPI Controller
> > Specification Rev 2.0
> > #7.17.2, Ultra DMA Data Transfer Speed list
> > For all Ultra DMA mode, MB, MC = 01h, 01h
I think that this patch is going in the right direction but it needs to also
take care of 66MHz internal clock setting:
* Please note that the same docs say that "For all Ultra DMA modes, 66MHz
internal clock will be used instead of 33MHz internal clock." and that this
is not true in case of Linux drivers.
* PDC20246 has no 66MHz internal clock AFAIK so those changes should not be
applied for this controller.
> > Are there other pdc202xx old controllers that are different?
>
> There are PDC20262 and PDC20246. We should ask Bart -- he probably has
> the documatation for them...
He doesn't, unfortunately..
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