+static u8 ep93xx_ide_readb(unsigned long base, unsigned long addr)
+{
+ u32 reg;
+
+ reg = ((addr & 0x07) << 2) | ((addr >> 3) & 0x03) | IDECTRL_DIORN |
+ IDECTRL_DIOWN;
+ writel(reg, IDE_REGISTER(IDECTRL));
+ ndelay(25);
+
+ reg &= ~IDECTRL_DIORN;
+ writel(reg, IDE_REGISTER(IDECTRL));
+ ndelay(70);
+
+ while (!ep93xx_ide_check_iordy())
+ cpu_relax();
+
+ reg |= IDECTRL_DIORN;
+ writel(reg, IDE_REGISTER(IDECTRL));
+ ndelay(25);
+
+ return readl(IDE_REGISTER(IDEDATAIN));
Hey, how this even works (if the data doesn't get latched
somehow)?! You
should read the register right *before* the deassertion of -DIORx! The
minimum data hold time is only 5 ns and the data lines will be tristated
within 30 ns maximum...
EP93xx User's Guide, Section 27 - 14 (IDEDataIn register Description)
<quote>:
"In PIO mode read operation, this register is the Input Data Registers,
containing the register contents or the data read from the device. The
register is loaded from the DD pins at the positive edge of the DIORn
signal. The register is read-only in this operation. ... "
Meaning, the data is latched from the data bus at the positive edge of
DIORn, and transfered into the IDEDATAIN register.
The above procedure is correct, according to this.
[...]
+static void
+ep93xx_ide_writeb(unsigned long base, u8 value, unsigned long addr)
+{
+ u32 reg;
+
+ reg = ((addr & 0x07) << 2) | ((addr >> 3) & 0x03) | IDECTRL_DIORN |
+ IDECTRL_DIOWN;
+ writel(reg, IDE_REGISTER(IDECTRL));
+ ndelay(25);
+
+ writel(value, IDE_REGISTER(IDEDATAOUT));
Hum, do you know at which moments this controller starts/stops driving
data lines on the IDE bus? After DIOWx- assertion/deassertion?
I will look into that. I based this source code in the CPU's user guide,
which tips a correct procedure for reading/writing in PIO mode.
But I will check that, as I already had some trouble with the user's
guide...
EP93xx User's Guide, Section 27 - 13 (IDEDataOut register Description)
<quote>:
"In PIO mode write operation, this register is the Output Data
Registers, containing the register contents or the data to be written to
the device. The register is driven onto the DD pins when DIOWn is low.
The register is both read write in this operation. ..."
Meaning, according to this, the procedure is correct. First we prepare
the data in the IDEDATAOUT register, then we assert DIOWn and data from
IDEDATAOUT is transfered to the data bus.
Regards,
João
--
************************************************************************
João Ramos <joao.ramos@xxxxxxx>
INOV INESC Inovação - ESTG Leiria
Escola Superior de Tecnologia e Gestão de Leiria
Edíficio C1, Campus 2
Morro do Lena, Alto do Vieiro
Leiria
2411-901 Leiria
Portugal
Tel: +351244843424
Fax: +351244843424
************************************************************************
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