JosephChan@xxxxxxxxxx wrote:
>>> + if (ap->port_no == 0 && pdev->device == 0xC409) {
>>> + pci_read_config_dword(pdev, 0x52, &ata66);
>>> + return (ata66 & 0x10) ? ATA_CBL_PATA80 :
>> ATA_CBL_PATA40;
>>> + } else if (ap->port_no == 1 && pdev->device == 0xC409) {
>>> + DPRINTK("C409 only has one pata channel\n");
>>> + return ATA_CBL_PATA_UNK;
>>> + }
>> Eh.. can you add 0xC409 entry like other controllers and put
>> necessary restrictions there?
>>
>
> It's a pity that we don't have corresponding registers for
> identifying the single port controller. So, we just can do this by
> checking the device ID at present.
I feel a bit confused so please correct me if I'm babbling. Can't you
add { PCI_VDEVICE(VIA, 0xC409), FLAGS_OR_IDENTIFIER } to pci_device_id
table and use different port_info on it? If that's too different from
how other devices are beign identified, you can just add the
corresponding logic to init_one() and use, say, via_single_port_info
there instead of doing it deep in the reset sequence.
>>> static void via_tf_load(struct ata_port *ap, const struct
>>> ata_taskfile *tf) {
>>> - struct ata_taskfile tmp_tf;
>>> + struct ata_ioports *ioaddr = &ap->ioaddr;
>>>
>>> - if (ap->ctl != ap->last_ctl && !(tf->flags &
>> ATA_TFLAG_DEVICE)) {
>>> - tmp_tf = *tf;
>>> - tmp_tf.flags |= ATA_TFLAG_DEVICE;
>>> - tf = &tmp_tf;
>>> + if (tf->ctl != ap->last_ctl) {
>>> + iowrite8(tf->ctl, ioaddr->ctl_addr);
>>> + iowrite8(tf->device, ioaddr->device_addr);
>>> }
>>> +
>>> ata_sff_tf_load(ap, tf);
>> Can you please explain why this change is necessary? And if
>> it's necessary, please put it in a separate patch.
>>
>
> Yes, I will separate it.
Thanks.
--
tejun
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