Hello.
Robert Hancock wrote:
This matters for some controllers and in one or two cases almost doubles
PIO performance. Add a bmdma32 operations set we can inherit and
activate
it for some controllers
Signed-off-by: Alan Cox <alan@xxxxxxxxxx>
---
drivers/ata/ata_piix.c | 2 +-
drivers/ata/libata-sff.c | 53
+++++++++++++++++++++++++++++++++++++++++++++
drivers/ata/pata_ali.c | 6 +++--
drivers/ata/pata_amd.c | 4 ++-
drivers/ata/pata_mpiix.c | 3 ++-
drivers/ata/pata_sil680.c | 4 ++-
include/linux/libata.h | 3 +++
7 files changed, 66 insertions(+), 9 deletions(-)
This can likely be enabled for more controllers (presumably all the
SFF-based SATA controllers as well as any other PATA that couldn't be
on a physical ISA bus).
Why are you so sure? Some controllers only support 32-bit accesses
when prefetch is enabled, some may not support it at all...
This is a start though.
Don't some of the VLB controller drivers have their own private 32-bit
PIO implementation? Those should likely be updated to use this support.
You mean sequence of 3 reads of some non-datra register?
MBR, Sergei
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