Jeff, while I realize that Intel's documentation may not be consistent with anything more generic (which I don't know where to look for), this current behavior seems to contradict what Intel documents for ESB2: "23.3.1.4 PI – Ports Implemented Register (D31:F2) Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO Default Value: 00000000h Size: 32 bits This register indicates which ports are exposed to the Intel® 631xESB/632xESB I/O Controller Hub. It is loaded by platform BIOS. It indicates which ports that the device supports are available for software to use. For ports that are not available, software must not read or write to registers within that port." Could you shed any extra light on this? Thanks, Jan - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
