On Sun, Dec 09 2007, Linus Torvalds wrote:
>
>
> On Sun, 9 Dec 2007, Robert Hancock wrote:
> >
> > The obvious suspect with a filesystem problem would be the disk
> > controller driver, AHCI here. However, the controller appears to set the
> > flag to indicate that it supports 64-bit DMA, so it should be fine,
> > unless it lies of course (which we know that ATI SB600 chipset does, but
> > I don't believe Intel is known to).
> >
> > Could still be a DMA mapping bug that only shows up when IOMMU is used.
> > However, AHCI is a pretty well tested driver..
>
> AHCI is a pretty well tested driver, but 99%+ of all testers still tend to
> have less than 4GB of memory. So I do *not* believe that the highmem bits
> are all that well tested at all.
>
> Can somebody who knows the driver send Marco a test-patch to just limit
> DMA to the low 32 bits, and then Marco can at least verify that yes, that
> that it. While it looks like DMA problems, there could obviously be some
> other subtle issue with big-memory machines (ie the PCI allocations etc
> tend to change too!)
Was just thinking that, this should do the trick. If this works, then we
can look at whether this is a hardware or iommu or block bouncing
(unlikely, would affect more people) bug.
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 4688dbf..cad3cbc 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -623,6 +623,9 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
+ hpriv->saved_cap &= ~HOST_CAP_64;
+ cap &= ~HOST_CAP_64;
+
/* some chips have errata preventing 64bit use */
if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
dev_printk(KERN_INFO, &pdev->dev,
--
Jens Axboe
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