On Thu, Nov 08, 2007 at 07:34:22PM +0800, jameshsu wrote: > From: LaurenceWu > We didn't study about ata/ahci.c, but it should be based on AHCI1.0 or 1.1 > spec. That is, NO P.M. FIS base switching, but supports both non-NCQ and NCQ > protocols. > > For NCQ or nonNCQ, 8620 is very AHCI-like, although not fully compatible, > programmer can easily modify standard ahci.c > for 8620. The main differences between 8620 and AHCI are : > > 1. PRD table format changed, (please compare AHCI 1.x section 4.2.3.3 and > 8620 datasheet section 7.3), 'I' bit in 8620 is defined as 'EOT' and NO > PRDTL value are available in the > Command List Structure. > > 2. For NCQ transfer, PxIS bit 3(SDBS) is changed. ATP8620 add the Reg_144h > to accumulate 32 Sactive bits in each SDB FIS. > The Reg_144h is RWC and all its 32 bits are 'ORed' to form the PxIS > bit3 and interrupt, if PxIE bit 3 enabled. > > Yes. Modifying the ata/ahci.c is OK to support atp8620. This is good information, thanks. After studying the datasheet I also noted a couple differences: 1) Port Multiplier support appears different from standard AHCI. 2) This chip includes target mode support. Very nice, well done! I hope that standard AHCI eventually supports this nice feature! Jeff - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
