> Yes, hence the recent FIFO drain patches. > > But that doesn't make sense for SATA devices, where the FIFO is really > emulated, and it works on older PATA devices. The FIFO is emulated on PATA. Basically speaking the device prefetches data and buffers the irq arrival until the right moment. Hence the need to drain it on some chips. Others reset themselves in this case and post reset a data read on some promise chips hangs the bus solid - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
