Hello, ICH9 has DeviceID's for 2 port, IDE mode, SATA controllers. The current port map in ata_piix is setup for the 4 port controllers. This seems to work ok, but I wonder if a new port map should be defined for the 2 port controllers, where the two ports are PM, SM? You can refer to the ICH9 Datasheet on intel.com for detail. Currently, ata_piix has ICH9 using this: static const struct piix_map_db ich8_map_db = { .mask = 0x3, .port_enable = 0x3, .map = { /* PM PS SM SS MAP */ { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ { RV, RV, RV, RV }, { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ { RV, RV, RV, RV }, }, }; Thanks, Jason - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html