No real performance change, but the # of unaligned kernel goes from ~14
to zero on my system.
It's really just cosmetic I believe.
...tom
Tejun Heo wrote:
Tom Evans wrote:
In sil24_config_port, the writel's for /* zero error counters */ should
be writew's - they are 16bit control registers.
Only PORT_DECODE_ERR_THRESH and PORT_CRC_ERR_THRESH appear to be
unaligned, but why risk a stl when a stw (on platforms that support it)
can be used.
That part of the code was taken verbatim from the Silicon Image sample
driver, which I'm sure have been tested only on x86s. Those error
threshold feature isn't really used and using writew's should be fine.
Do things work better after changing to writew's?
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