Hello, I wrote:
Does anyone have any decent information on the purpose, performance
potential
or perhaps quirks of the "read prefetch" and "post write" buffer
features on
some IDE chipsets?
Oh, I've forgotten to reply about posting. :-)
There's a (little) wrtie post buffer in the IDE contoroller where it
puts the data from the PCI and GNTs the PCI transfer. The data later
Perhaps I've used GNT incorrectly: it seems to be a signal between a
master PCI device and PCI arbiter.
So, the write buffer just helps to teminate PCI write(s) earlier than the
data arrive to the drive.
MBR, Sergei
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