Bob Ham wrote:
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask including mode 5 used to check for the necessity of 66 MHz clocking -- This caused 66 MHz clock to be used for HPT374 chip that does not tolerate it. While fixing this, also remove PLL mode from the TODO list -- I don't think it's still relevant item.
Signed-off-by: Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx>
--- This is against the current Linus tree. Bob, please test it and report what you'll find out...
para_hpt37x: bus clock 33MHz, using 50MHz DPLL.
Aha, note that 33 MHz PCI clock is now reported.
ACPI: PCI Interrupt 0000:00:0d.0[A] -> GSI 16 (level, low) -> IRQ 17 scsi2: pata_hpt37x scsi3: pata_hpt37x ata3: PATA max UDMA/100 cmd 0x0001efa0 ctl 0x0001ef9e bmdma 0x0001ec00 irq 17 ata4: PATA max UDMA/100 cmd 0x0001ef90 ctl 0x0001ef9a bmdma 0x0001ec00 irq 17
followed by a hard lock
Well, so it's tougher than just that but the patches are good anyway. Wait... doesn't it get stuck trying to pick up the HPT374 chip's function 1?
MBR, Sergei - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
