Alan Cox wrote:
I am reluctant to do anything about this.
This one does need dealing with. It happens in the real world and the old
IDE paths for this do get triggered and used now and then (we know this
because bugs in them were found). All it takes is a device and a
controller disagreeing about the length of a data transfer to get in a
How would they disagree (excluding human error)?
mess. In theory resetting the bus should get you out of this, I'm
suprised we didn't get out that way.
Indeed.
All manner of things can go wrong, if the taskfile protocol specified
disagrees with the taskfile contents.
True but at the point you are trying to do error recovery and DRQ is
wedged on its a good idea to pull remaining data out of the fifo.
It's not really a good idea for SATA. The "FIFO" often co-emulated by
the SATA controller and SATA phy. You just want to kick SATA really
hard (i.e. bus reset and friends).
Jeff
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