Re: Question about PATA Sil680 Cache Line Size and Performance Degradation on ARM XScale

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Alan wrote:
Since Sil3124 has better PCI read/write performance, as a reference,
could someone explain or point me to the PCI configuration code for
Sil3124? I couldn't find it in sata_sil24.c.

Are you sure the values used are not the power on ones in this case ?

The values used, most likely, are BIOS-programmed.

sata_sil24.c does not call pci_set_mwi(), which is the only code in the kernel (besides driver-specific, hand-coded stuff) that adjusts the PCI cacheline register value.

	Jeff



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