Hello. Segher Boessenkool wrote:
--- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -1234,6 +1234,14 @@ static void __devinit fixup_resource(str struct pci_controller *hose = pci_bus_to_host(dev->bus); unsigned long start, end, mask, offset; + /* + * tell the core code that this ressource is unassigned + * fixes p630 winbond IDE with libata + */ + if (res->start == 0) { + res->flags = 0; + return; + } if (res->flags & IORESOURCE_IO) { offset = (unsigned long)hose->io_base_virt - pci_io_base;Please make this run on pSeries only; on a PowerMac for example, it's totally normal that the first PCI legacy I/O BAR in the system gets assigned 0.
What do you mean by legacy I/O BAR? If you mean IDE controller, that would drive IDE core mad like this:
W82C105_IDE: inconsistent baseregs (BIOS) for port 0, skipping
Segher
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