> > static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
> > {
> > struct ata_host *host = dev_instance;
> > int i, handled = 0;
> > + u32 notifier_clears[2];
> >
> > spin_lock(&host->lock);
> >
> > for (i = 0; i < host->n_ports; i++) {
> > struct ata_port *ap = host->ports[i];
> > + notifier_clears[i] = 0;
>
> Promise us that n_ports will never exceed 2?
I promise it will never exceed 2, at least as far as NVIDIA ADMA
hardware is concerned.
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