On Fri, Jun 02, 2006 at 03:44:55PM +0800, zhao, forrest wrote:
> +static int ahci_stop_fis_rx(void __iomem *port_mmio)
> +{
> + u32 tmp;
> + int work = 1000;
> +
> + /*
> + * Get current status
> + */
> + tmp = readl(port_mmio + PORT_CMD);
> +
> + /* Check if FIS RX is already disabled */
> + if ((tmp & PORT_CMD_FIS_RX) == 0)
> + return 0;
> +
> + /*
> + * AHCI Rev 1.1 section 10.3.2
> + * Software shall not clear PxCMD.FRE while
> + * PxCMD.ST or PxCMD.CR is set to '1'
> + */
> + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_START)) {
> + return -EPERM;
> + }
Same here. I'm not sure whether the above two tests are necessary,
but that might be just me. :)
> + /*
> + * Disable FIS reception
> + *
> + * AHCI Rev 1.1 Section 10.1.2:
> + * If PxCMD.FRE is set to '1', software should clear it
> + * to '0' and wait at least 500 milliseconds for PxCMD.FR
> + * to return '0' when read. If PxCMD.FR does not clear
> + * '0' correctly, then software may attempt a port reset
> + * of a full HBA reset to recover.
> + */
> + tmp &= ~(PORT_CMD_FIS_RX);
> + writel(tmp, port_mmio + PORT_CMD);
> +
> + mdelay(500);
> + work = 1000;
> + while (work-- > 0) {
> + tmp = readl(port_mmio + PORT_CMD);
> + if ((tmp & PORT_CMD_FIS_ON) == 0)
> + return 0;
> + udelay(10);
> + }
Please convert to ata_wait_register(). Also, I share Jens' opinion.
The way I read the spec is that the timeout should be at least 500ms
not that we have to wait 500ms before polling for !FIS_ON.
--
tejun
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