Tejun Heo wrote:
Tejun Heo wrote:
Jeff Garzik wrote:
Actually, looking even more at the code, I think the entire
"spurious interrupt" code block is bogus.
The device is free to send D2H or SDB FIS to clear Status bits, as
well as SDB FIS's to update SActive. The ata_qc_complete_multiple()
call will do the right thing, even if there is no work to do.
Yes, they are, but...
* Please note that SActive update via SDB FIS is edge-triggered. It
doesn't send the whole image of the register. The SActive bits in
SDB FIS indicate W1C (this is inevitable because controller and
device cannot be in full synchronization regarding SActive). So,
they have can have dangerous side effects.
* Those spurious FISes are actively setting the I bit requesting
interrupt explicitly. Those are not innocent status update FISes.
And the spec state machines don't allow D2H FISes during NCQ command
phase. I seem to recollect it's actually forbidden explicitly but
currently cannot find where. I'll keep looking.
Oops, strike out the part about D2H not allowed. It certainly is
allowed to clear BSY. Sorry.
(Trying to keep up ;-))
Is there still value in testing your last patch?
ric
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