On Llu, 2006-05-15 at 22:59 +0900, Tejun Heo wrote: > I see. But even with the shared IRQ, unconditionally clearing IRQ for > short duration wouldn't cause much problem, would it? Clearing in what sense. If you just clear it then you may well just get another one. If you ack it on the hardware then you need to recover anything that may be lost before the next IRQ. Wouldn't think its a big problem with BMDMA at all. If a given channel interrupts us then we know what state it is in and we also know there are no other outstanding commands even possible on the device. Since you freeze the device not the channel (at least if I read the code right for native mode paths) this ought to be fine. Legacy mode you freeze the channel but there is a per channel IRQ (and the per channel host needs fixing anyway). The same need to clean up is true btw of PIO. Several controllers have errata if you read a control register during a PIO transfer so you must halt the PIO block transfer first. Intel PIIX4/440MX have this problem. > @ Out of curiosity, how old does a controller have to be to not have the > ctl shadow register? You'll find controllers today that don't appear to have one (eg cf flash) - : send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
