Hi, On 25/06/14 23:23, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:+ coherency_line_size: the minimum amount of data that gets transferredSo, what value to do envision this taking for a CPU where the cache line size is 32 bytes, but each cache line has two dirty bits which allow it to only evict either the upper or lower 16 bytes depending on which are dirty?
IIUC most of existing implementations of cacheinfo on various architectures are representing the cache line size as coherency_line_size, in which case I need fix the definition in this file. BTW will there be any architectural way of finding such configuration ? Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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