Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
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- To: Sudeep Holla <sudeep.holla@xxxxxxx>
- Subject: Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
- From: Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx>
- Date: Wed, 25 Jun 2014 23:23:56 +0100
- Cc: linux-kernel@xxxxxxxxxxxxxxx, Rob Herring <robh@xxxxxxxxxx>, linux-s390@xxxxxxxxxxxxxxx, Lorenzo Pieralisi <Lorenzo.Pieralisi@xxxxxxx>, linux-ia64@xxxxxxxxxxxxxxx, linux-doc@xxxxxxxxxxxxxxx, Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, x86@xxxxxxxxxx, Heiko Carstens <heiko.carstens@xxxxxxxxxx>, linux390@xxxxxxxxxx, linuxppc-dev@xxxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
- In-reply-to: <1403717444-23559-3-git-send-email-sudeep.holla@arm.com>
- List-id: <linux-ia64.vger.kernel.org>
- References: <1403717444-23559-1-git-send-email-sudeep.holla@arm.com> <1403717444-23559-3-git-send-email-sudeep.holla@arm.com>
- User-agent: Mutt/1.5.19 (2009-01-05)
On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:
> + coherency_line_size: the minimum amount of data that gets transferred
So, what value to do envision this taking for a CPU where the cache
line size is 32 bytes, but each cache line has two dirty bits which
allow it to only evict either the upper or lower 16 bytes depending
on which are dirty?
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