On Mon, Feb 09, 2009 at 04:33:24PM -0700, Alex Chiang wrote: > > I'm a little closer to understanding why the original revert > survives my test though. > > It seems that during ia64_process_pending_intr(), we will skip > TLB flushes, and IPI reschedules. > > Vectors lower than IA64_TIMER_VECTOR are masked (because we raise > the TPR), meaning we won't see CMC/CPE interrupts or perfmon > interrupts. > > This leaves only IPIs and MCA above IA64_TIMER_VECTOR. The kernel > doesn't actually send many IPIs to itself, so in practice, we > almost never see those. If we receive an MCA interrupt, well, we > have more problems to worry about than taking a CPU offline (and > whatever implications it may have on RCU). So I'm not concerned > there. Keep in mind there are recoverable MCAs on ia64. It should be a rare condition to have an MCA surface while taking a CPU offline, but it could happen. My main point is to make sure people do not assume that an MCA means the system is going down. > The upshot is that in practice, we pretty much ever only need to > handle the timer interrupt. Thanks. -- Russ Anderson, OS RAS/Partitioning Project Lead SGI - Silicon Graphics Inc rja@xxxxxxx -- To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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