> I was thinking about a case where the TLB is shared (SMT) between linux > logical CPUs (threads) but ia64 is not SMT right ? Thus the TLB is > split ,and the "other" CPU can't see the stale translation... should be > allright then. Montecito is SMT, and the threads do share the TLB resources in that there are a fixed number of TLB TC slots that are dynamically shared between threads. But entries in the TLB have their virtual addresses tagged with a thread identifier, so an entry inserted by one thread cannot be used by another thread. See sections 2.4.3.1.1 and 2.4.3.1.2 in "Dual-Core Update to the Intel® Itanium® 2 Processor Reference Manual" http://download.intel.com/design/Itanium2/manuals/30806501.pdf -Tony - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
|