On Thu, 2007-08-02 at 17:10 +1000, Benjamin Herrenschmidt wrote: > On Wed, 2007-08-01 at 22:38 -0700, Luck, Tony wrote: > > No locking. But we do have race detection. After we chase the > > PGD>PUD>PMD>PTE > > pointers we insert the TLB entry. Then we retrace the pointer chain > > and > > make sure that the pte we find is still the same. If it isn't, then > > we > > purge the entry we just inserted and go for a full page fault. > > > > Time to tell bed-time stories to my daughter. More tomorrow (if > > someone > > else doesn't fill in the rest of the answers before I get back to > > this). > > Ok, that's what I think I understood from the asm. However, what > prevents the very unlikely race where you insert a stale pgtable > mapping entry, and before you backtrack and remove it, another > CPU accesses the stale PTE ? I was thinking about a case where the TLB is shared (SMT) between linux logical CPUs (threads) but ia64 is not SMT right ? Thus the TLB is split ,and the "other" CPU can't see the stale translation... should be allright then. Cheers, Ben. - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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