Christoph Lameter wrote:
Could you measure the effect that this has? We seem to be getting into some special processor behavior here.
Telling the truth: I cannot measure it. The architecture ia64 defines some hints which *may* increase the performance. If you have a sequence that does not cost a penny and may run faster... If you have a shorter and somewhat faster sequence because of the elimination of "cmp" that had to wait the completion the "cmpxchg"... ... why not?
The last that I heard about nta was that it just skips the marking of a cacheline as recent. Thus the cacheline will be a more likely candidate to be evicted from the caches. Are you sure that the processors can bypass the L1D and L3?
Please refer to e.g. the I2 Proc. Ref. Man. for SW Dev. & Opt. - may 2004 table 5-4 on page 41. Thanks, Zoltan - : send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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