On Mon, 13 Mar 2006, Zoltan Menyhart wrote: > I think we can do some accessed/dirty bit handler tuning. E.g. > in my patch (based on the Christoph's one entitled "Fix race in the > accessed/dirty bit handlers"), I think we gain a bit by: Could you measure the effect that this has? We seem to be getting into some special processor behavior here. > - using the "nta" hint in order not to "pollute" the caches L1D / L3 The last that I heard about nta was that it just skips the marking of a cacheline as recent. Thus the cacheline will be a more likely candidate to be evicted from the caches. Are you sure that the processors can bypass the L1D and L3? - : send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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