Hi, On Mon, Dec 23, 2024 at 06:35:28AM +0000, Lad, Prabhakar wrote: > On Sun, Dec 22, 2024 at 12:44 PM Wolfram Sang > > > ● Write: > > > 0: Changes the RIICnSCL/RIICnSDA pin output to a low level. > > > 1: Changes the RIICnSCL/RIICnSDA pin in a high-impedance state. > > > (High level output is achieved through an external pull-up resistor.) > > > > > > So using the generic algorithm may be platform dependent as it would > > > only work on platforms which have external pull-up resistor on SDA/SCL > > > pins. So to overcome this and make recovery possible on the platforms > > > I choose the RIIC feature to output clock cycles as required. > > > > I would be super-surprised if this is really a restriction and not a > > very precise documentation. In other words, I am quite sure that there > > is no difference between the bit forcing SCL high (via high-impedance) > > and the internal RIIC handling when it needs SCL high. Most I2C busses > > are open-drain anyhow. > > > I had asked this previously to the HW engineers about the requirement > (as this restriction is not mentioned in the RZ/V2H(P) SoC, Ive seen > it for RZ/A series RZ/G2L family and RZ/G3S only) before the start of > the I2C recovery work but haven't got a response yet. Ive pinged them > again and I'll wait for their feedback. Wolfram has commented on a very valid point, on a standard i2c specification. I'd like to merge this once all the hardware questions are answered. Please, do follow up on this. Thanks, Andi
