Enable DWAPB I2C controller support on FUJITSU-MONAKA.
This will be used in the FUJITSU-MONAKA server scheduled
for shipment in 2027.
The DSDT information obtained when verified using an
in-house simulator is presented below.
Device (SMB0)
{
Name (_HID, "FUJI200B") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
...
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0x2A4B0000, // Address Base
0x00010000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000159,
}
})
...
}
The expression SMB0 is used to indicate SMBus HC#0,
a string of up to four characters.
Created the SMB0 object according to the following
specifications:
ACPI Specification
13.2. Accessing the SMBus from ASL Code
https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/13_ACPI_System_Mgmt_Bus_Interface_Spec/accessing-the-smbus-from-asl-code.html
IPMI Specification
Example 4: SSIF Interface(P574)
https://www.intel.co.jp/content/www/jp/ja/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
Signed-off-by: Yoshihiro Furudera <fj5100bi@xxxxxxxxxxx>
---
Changes in v2:
- Updated the commit message as per previous discussion. (Andy)
- Change the string "Fujitsu MONAKA" to "FUJITSU-MONAKA"
- Link to v1: https://lore.kernel.org/all/20241018015826.2925075-1-fj5100bi@xxxxxxxxxxx/
drivers/i2c/busses/i2c-designware-platdrv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 2d0c7348e491..c04af315a4f9 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -351,6 +351,7 @@ static const struct acpi_device_id dw_i2c_acpi_match[] = {
{ "AMDI0019", ACCESS_INTR_MASK | ARBITRATION_SEMAPHORE },
{ "AMDI0510", 0 },
{ "APMC0D0F", 0 },
+ { "FUJI200B", 0 },
{ "HISI02A1", 0 },
{ "HISI02A2", 0 },
{ "HISI02A3", 0 },
--
2.34.1
