Hi, Geert,
On 24.06.2024 18:40, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Fri, Jun 21, 2024 at 1:23 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
>> the version available on Renesas RZ/V2H (R9A09G075). Most of the IP
>> variants that the RIIC driver is working with supports fast mode plus.
>> However, it happens that on the same SoC to have IP instatiations that
>> support fast mode plus as well as IP instantiation that doesn't support
>> it. For this, introduced the renesas,riic-no-fast-mode-plus property.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> @@ -25,6 +25,10 @@ properties:
>> - renesas,riic-r9a07g054 # RZ/V2L
>> - const: renesas,riic-rz # RZ/A or RZ/G2L
>>
>> + - items:
>> + - const: renesas,riic-r9a08g045 # RZ/G3S
>> + - const: renesas,riic-r9a09g057
>> +
>
> LGTM.
>
>> - const: renesas,riic-r9a09g057 # RZ/V2H(P)
>>
>> reg:
>> @@ -66,6 +70,10 @@ properties:
>> resets:
>> maxItems: 1
>>
>> + renesas,riic-no-fast-mode-plus:
>> + description: specifies if fast mode plus is not supported
>> + type: boolean
>> +
>
> Do you really need this?
> The bus' clock-frequency property should take into account the combined
> capabilities of all of controller, target, and wiring. It is up to the
> DTS writer to validate that all timing conditions are met.
On a second thought, I tend to agree with you on this.
I added it to comply with "chapter 47.5.15 I2C Bus Interface Access
Timing, note 7, Tfmin cannot meet the specification in fast-mode plus for
the RIIC ch2 and ch3" statement from hw manual.
Thank you,
Claudiu Beznea
>
>> required:
>> - compatible
>> - reg
>
> Gr{oetje,eeting}s,
>
> Geert
>
