On Wed, Jan 31, 2024 at 04:16:46PM +0200, Jarkko Nikula wrote: > Hi Jiawen, Sanket and Basavaraj > > Could you test on your Wangxun 10Gb NIC and AMD NAVI GPU harware this > patchset since it's touching both. > > For the AMD NAVI GPU and changes are less but for the Wangxun 10Gb NIC > patchset replaces the txgbe_i2c_dw_xfer_quirk() with generic polling mode > code. > > I've been testing this on our HW which all have interrupt connected and > tried to cover also FIFO depth defines for Wangxun 10Gb NIC. Obviously I > would like to know how this set works on your real HW. ... > Jarkko Nikula (6): > i2c: designware: Uniform initialization flow for polling mode > i2c: designware: Do not enable interrupts shortly in polling mode > i2c: designware: Use accessors to DW_IC_INTR_MASK register > i2c: designware: Move interrupt handling functions before > i2c_dw_xfer() > i2c: designware: Fix RX FIFO depth define on Wangxun 10Gb NIC > i2c: designware: Implement generic polling mode code for Wangxun 10Gb > NIC Last two patches named the same, Something is screwed up. -- With Best Regards, Andy Shevchenko
