Hi Alexander, Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> writes: > I assume that the master clock is running independently to I2C from the SoC > the sensor is attached to. Your calculations indicate you are assuming ~400kHz > I2C clock frequency. This is correct. > But nothing is preventing that sensor from running on a 100kHz I2C bus. Even > this "atomic" hack will not be sufficient in that case. It will be sufficient. Even if all times are 4x longer (they shouldn't since the CPU won't get slower), they wouldn't reach, say, 1200 us. There would still be quite a lot of a margin (the timeout is 7 ms). Even with the faster MCLK (these sensors can operate on 37.125 and on 74.250 MHz) and IF the timeout is still 2^18 in the latter case (meaning 3.5 ms), it would most probably work. Of course, the atomic hack is not meant for general consumption (at least for now in its current shape), only the udelay() reduction (100 -> 1) could probably go in. -- Krzysztof "Chris" Hałasa Sieć Badawcza Łukasiewicz Przemysłowy Instytut Automatyki i Pomiarów PIAP Al. Jerozolimskie 202, 02-486 Warszawa
