Hi Krzysztof, > -----Original Message----- > From: Krzysztof Adamski <krzysztof.adamski@xxxxxxxxx> > Sent: Wednesday, June 29, 2022 6:44 PM > To: Manikanta Guntupalli <manikanta.guntupalli@xxxxxxxxxx>; > michal.simek@xxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; linux- > arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-i2c@xxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx> > Cc: Srinivas Goud <srinivas.goud@xxxxxxxxxx> > Subject: Re: [PATCH 12/12] i2c: xiic: Correct the BNB interrupt enable > sequence > > CAUTION: This message has originated from an External Source. Please use > proper judgment and caution when opening attachments, clicking links, or > responding to this email. > > > W dniu 24.06.2022 o 14:05, Manikanta Guntupalli pisze: > > From: Srinivas Goud <srinivas.goud@xxxxxxxxxx> > > > > With updated AXI IIC IP core(v2.1)there is change in IP behavior in > > dynamic mode, where controller initiate read transfer on IIC bus only > > after getting the value for the number of bytes to receive. > > > > In the existing xiic_start_recv function Bus Not Busy(BNB) interrupt > > is enabled just after "slave address + start" > > write to FIFO and before the "count + stop"write to FIFO. > > Since IIC controller drives the start address of a transaction on the > > bus only after it has received the byte count information the above > > sequence can lead to spurious BNB interrupt in case there is any delay > > after "slave address + start" write to FIFO. > > > > This is fixed by ensuring that BNB interrupt is enabled only after > > "count + stop" has been written to FIFO. > > > > Signed-off-by: Srinivas Goud <srinivas.goud@xxxxxxxxxx> > > Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@xxxxxxxxxx> > > --- > > [...] > > Does this spurious interrupt cause any trouble or it is just ignored and the > only problem is unneeded extra CPU load? > No functional issue we just corrected the sequence as per IP changes. > Krzysztof Thanks, Manikanta.
