On Thu, 2022-06-16 at 05:17 +0000, Datta, Shubhrajyoti wrote: > [AMD Official Use Only - General] > > Hi , > Thanks for the patch > > -----Original Message----- > > From: Robert Hancock <robert.hancock@xxxxxxxxxx> > > Sent: Wednesday, June 15, 2022 4:59 AM > > To: linux-i2c@xxxxxxxxxxxxxxx > > Cc: Raviteja Narayanam <rna@xxxxxxxxxxxxxxx>; Michal Simek > > <michals@xxxxxxxxxx>; Anurag Kumar Vulisha <anuragku@xxxxxxxxxx>; > > wsa@xxxxxxxxxx; Shubhrajyoti Datta <shubhraj@xxxxxxxxxx>; Robert > > Hancock <robert.hancock@xxxxxxxxxx> > > Subject: [PATCH] i2c: cadence: Change large transfer count reset logic to > > be > > unconditional > > > > Problems were observed on the Xilinx ZynqMP platform with large I2C reads. > > When a read of 277 bytes was performed, the controller NAKed the transfer > > after only 252 bytes were transferred and returned an ENXIO error on the > > transfer. > > > Can you help me reproduce the issue what is the command that you used to get > the failure. The actual failure I was seeing was in the tests for the PKCS#11 library implementation for the Infineon Optiga Trust M HSM device: https://github.com/Infineon/pkcs11-optiga-trust-m Some of the tests involve reading generated RSA keys from the device and so result in such long I2C reads. However, you could probably use any I2C device which can support such a long read using a command such as: i2ctransfer 0 r300@0x61 for address 0x61. The behavior where only 252 bytes was transferred was seen using a logic analyzer on the I2C bus. -- Robert Hancock Senior Hardware Designer, Calian Advanced Technologies www.calian.com
