On Tue, Mar 09, 2021 at 09:42:52AM +0100, Henning Schild wrote: > Am Mon, 8 Mar 2021 19:42:21 -0600 > schrieb Bjorn Helgaas <helgaas@xxxxxxxxxx>: > > On Mon, Mar 08, 2021 at 09:16:50PM +0200, Andy Shevchenko wrote: > > > On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote: > > > > On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote: ... > > > > > + /* Read the first BAR of the device in question */ > > > > > + __pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, > > > > > PCI_BASE_ADDRESS_0, true); > > > > > > > > I don't get this. Apparently this normally hidden device is > > > > consuming PCI address space. The PCI core needs to know about > > > > this. If it doesn't, the PCI core may assign this space to > > > > another device. > > > > > > Right, it returns all 1:s to any request so PCI core *thinks* it's > > > plugged off (like D3cold or so). > > > > I'm asking about the MMIO address space. The BAR is a register in > > config space. AFAICT, clearing P2SBC_HIDE_BYTE makes that BAR > > visible. The BAR describes a region of PCI address space. It looks > > like setting P2SBC_HIDE_BIT makes the BAR disappear from config space, > > but it sounds like the PCI address space *described* by the BAR is > > still claimed by the device. If the device didn't respond to that > > MMIO space, you would have no reason to read the BAR at all. > > > > So what keeps the PCI core from assigning that MMIO space to another > > device? > > The device will respond to MMIO while being hidden. I am afraid nothing > stops a collision, except for the assumption that the BIOS is always > right and PCI devices never get remapped. But just guessing here. > > I have seen devices with coreboot having the P2SB visible, and most > likely relocatable. Making it visible in Linux and not hiding it again > might work, but probably only as long as Linux will not relocate it. > Which i am afraid might seriously upset the BIOS, depending on what a > device does with those GPIOs and which parts are implemented in the > BIOS. So the question is, do we have knobs in PCI core to mark device fixes in terms of BARs, no relocation must be applied, no other devices must have the region? -- With Best Regards, Andy Shevchenko
