Hi
On 3/22/21 6:59 PM, Sanket Goswami wrote:
The Latest AMD NAVI GPU card has an integrated Type-C controller and
Designware I2C with PCI Interface. The Type-C controller can be
accessed over I2C. The client driver is part of the USB Type-C UCSI
driver.
Also, there exists a couple of notable IP limitations that are dealt as
workarounds:
- I2C transaction work on a polling mode as IP does not generate
interrupt.
- I2C read command sent twice to address the IP issues.
Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
Co-developed-by: Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@xxxxxxx>
Signed-off-by: Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@xxxxxxx>
Signed-off-by: Sanket Goswami <Sanket.Goswami@xxxxxxx>
---
Changes in v2:
- Utilized existing functionality of i2c_dw_xfer_init to configure I2C
bus.
- Removed i2c_dw_populate_client and rewrrient navi_amd_register_client
to deduplicate from existing drivers.
- Addressed review comments from Andy.
drivers/i2c/busses/i2c-designware-common.c | 3 +
drivers/i2c/busses/i2c-designware-core.h | 3 +
drivers/i2c/busses/i2c-designware-master.c | 136 +++++++++++++++++++++
drivers/i2c/busses/i2c-designware-pcidrv.c | 57 +++++++++
4 files changed, 199 insertions(+)
diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index 3c19aada4b30..50883a70b482 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -150,6 +150,9 @@ int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
reg = readl(dev->base + DW_IC_COMP_TYPE);
i2c_dw_release_lock(dev);
+ if (dev->flags & AMD_NON_INTR_MODE)
+ map_cfg.max_register = AMD_UCSI_INTR_REG;
+
if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
map_cfg.reg_read = dw_reg_read_swab;
map_cfg.reg_write = dw_reg_write_swab;
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 5392b82f68a4..f29923c452ac 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -293,9 +293,12 @@ struct dw_i2c_dev {
#define ACCESS_INTR_MASK BIT(0)
#define ACCESS_NO_IRQ_SUSPEND BIT(1)
+#define AMD_NON_INTR_MODE BIT(2)
#define MODEL_MSCC_OCELOT BIT(8)
#define MODEL_BAIKAL_BT1 BIT(9)
#define MODEL_MASK GENMASK(11, 8)
+#define AMD_UCSI_INTR_EN 0xd
+#define AMD_UCSI_INTR_REG 0x474
int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index dd27b9dbe931..a76e1f992850 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -23,6 +23,10 @@
#include "i2c-designware-core.h"
+#define AMD_TIMEOUT_MIN_MSEC 10000
+#define AMD_TIMEOUT_MAX_MSEC 11000
+#define AMD_MASTERCFG_MASK GENMASK(15, 0)
+
static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
{
/* Configure Tx/Rx FIFO threshold levels */
@@ -208,6 +212,13 @@ static int i2c_dw_init_master(struct dw_i2c_dev *dev)
if (dev->sda_hold_time)
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
+ /*
+ * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
+ * it is mandatory to set the right value in specific register
+ * (offset:0x474) as per the hardware IP specification.
+ */
+ if (dev->flags & AMD_NON_INTR_MODE)
+ regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
This confuses me - this patch is about adding support for DesignWare IP
that does not generate interrupts but here code is enabling an
interrupt. I guess it's for UCSI but should above code then go to a
driver handling that IP?
+static int i2c_dw_check_stopbit(struct dw_i2c_dev *i2cd)
...
+static int i2c_dw_status(struct dw_i2c_dev *i2cd)
...
+static int amd_i2c_dw_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
...
+{
+ struct dw_i2c_dev *i2cd = i2c_get_adapdata(adap);
For uniformity I'd use struct dw_i2c_dev *dev name instead of *i2cd
since that what driver uses currently in other places.
@@ -461,6 +587,13 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
pm_runtime_get_sync(dev->dev);
+ /*
+ * Initiate I2C message transfer when AMD NAVI GPU card is enabled,
+ * As it is polling based transfer mechanism, which does not support
+ * interrupt based functionalities of existing DesignWare driver.
+ */
+ if (dev->flags & AMD_NON_INTR_MODE)
+ return amd_i2c_dw_master_xfer(adap, msgs, num);
Does runtime PM go out of sync here?
Jarkko
