From: Linuxppc-dev Guenter Roeck > Sent: 11 March 2021 21:35 > > On 3/11/21 1:17 PM, Chris Packham wrote: > > > > On 11/03/21 9:18 pm, Wolfram Sang wrote: > >>> Bummer. What is really weird is that you see clock stretching under > >>> CPU load. Normally clock stretching is triggered by the device, not > >>> by the host. > >> One example: Some hosts need an interrupt per byte to know if they > >> should send ACK or NACK. If that interrupt is delayed, they stretch the > >> clock. > >> > > It feels like something like that is happening. Looking at the T2080 > > Reference manual there is an interesting timing diagram (Figure 14-2 if > > someone feels like looking it up). It shows SCL low between the ACK for > > the address and the data byte. I think if we're delayed in sending the > > next byte we could violate Ttimeout or Tlow:mext from the SMBUS spec. > > > > I think that really leaves you only two options that I can see: > Rework the driver to handle critical actions (such as setting TXAK, > and everything else that might result in clock stretching) in the > interrupt handler, or rework the driver to handle everything in > a high priority kernel thread. I'm not sure a high priority kernel thread will help. Without CONFIG_PREEMPT (which has its own set of nasties) a RT process won't be scheduled until the processor it last ran on does a reschedule. I don't think a kernel thread will be any different from a user process running under the RT scheduler. I'm trying to remember the smbus spec (without remembering the I2C one). While basically a clock+data bit-bang the slave is allowed to drive the clock low to extend a cycle. It may be allowed to do this at any point? The master can generate the data at almost any rate (below the maximum) but I don't think it can go down to zero. But I do remember one of the specs having a timeout. But I'd have thought the slave should answer the cycle correctly regardless of any 'random' delays the master adds in. Unless you are getting away with de-asserting chipselect? The only implementation I've done is one an FPGA so doesn't have worry about interrupt latencies. It doesn't actually support clock stretching; it wasn't in the code I started from and none of the slaves we need to connect to ever does it. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
