This patchset fixes various issues related to SCL rate on AML SoCs. We retain the method which was used so far to set the SCL rate. This method does not provide manual control of the clock duty cycle but so far it does seems to be a problem for anyone. Amlogic vendor kernel source uses "HIGH/LOW" method which allows to set the rate and the duty cycle of the clock. However the documentation around this method could be better and the result on actual HW is not perfectly aligned with the comments in AML code. In case the current method ever becomes a problem, we might consider switching to this HIGH/LOW method. Jerome Brunet (2): i2c: meson: fix clock setting overwrite i2c: meson: keep peripheral clock enabled Nicolas Belin (1): i2c: meson: fixup rate calculation with filter delay drivers/i2c/busses/i2c-meson.c | 52 +++++++++++++++++++++------------- 1 file changed, 33 insertions(+), 19 deletions(-) -- 2.25.4
